Elbrus S

Introduction

Elbrus-S is a system-on-chip, designed for the acquisition of computing resources in weapons systems, data-processing and control systems for industrial applications. Improved performance characteristics of the chip itself allowes for better memory capacity, faster input-output and an increase of the number of allowed processors in a multiprocessor system as of 4 or more.

• Elbrus-S includes one Elbrus 2000 processor core with 2 MB of cache memory, 2 memory controllers for access to local RAM, 3 controllers for interprocessor communications, access to other memory sections and controller for the I/O subsystem.
• The Elbrus 2000 core is a high performance general purpose microprocessor with a very long instruction word (VLIW) architecture, designed for the 90 nm technology, running at a clock speed of 500 MHz.
• Interprocessor communications and memory access is organized by a distributed switch, with has support for data and cache coherency in a distributed shared memory system.
• Elbrus-S provides support for running Intel x86 software, as defined by the Elbrus 2000 architecture.
• Elbrus-S provides support for secure computing, as defined by the Elbrus 2000 architecture.

Highlights

Process	90 nm
Clock frequency	500 MHz
Whole data width	8, 16, 32, 64
Real data width	80, 64, 32
Peak performance 64-bit (real arithmetic), vesch billion. op/sec	4
Peak performance 32-bit (real arithmetic), vesch billion. op/sec	8
Peak performance 16-bit (integer arithmetic), billion op/sec	8
Peak performance 8-bit (integer arithmetic), billion op/sec	16
Peak performance 64-bit (mixed calculations), billion op/sec	10
Peak performance 32-bit (mixed calculations), billion op/sec	16.5
Peak performance 16-bit (mixed calculations), billion op/sec	21.5
Peak performance 8-bit (mixed calculations), billion op/sec	39.5
Data cache, kB	64
Instruction cache, kB	64
Level 2 cache (universal), MB	2
Data cache page input	1024
Instruction cache page input	64
Bus bandwidth to the cache memory, GB/s	16
Bus bandwidth to the RAM (two channels), GB/s	8
Channel bandwidth interprocessor exchange, GB/s	12
Capacity of the I/O channel, GB/s	2
Number of transistors	218 million
Enclosure Type / number of pins	HFCBGA 1156
Case dimensions	35 x 35 x 3,2 mm
Supply voltage	1.1 / 1.8 / 2.5 V
Maximum power consumption	20 W
Typical power consumption	~13 W